The mass-storage market is currently dominated by magnetic hard drives, which can range in capacity up to a terabyte or more. In the gigabyte range, prior art solid-state Flash memory (FIG. 3) have been used by computing devices such as laptop computers and media players. However, hard drives contain movable parts, are generally slower, less robust, and consume more power than solid-state memory.
For Flash memories to achieve the storage capacity of hard drives, the storage element of a Flash memory would have to be reduced substantially in scale. However, at scales below 35 nm technology, a memory cell typically retains only a hundred (or fewer) electrons [1]. Such few stored electrons lead to significant statistical bit-to-bit variation, as well as poor charge retention, since long-term storage imposes drastic leakage current limits, of the order of one or two electrons per month. Another drawback of Flash memories is its high write/erase voltage (˜15 V), which is needed for tunneling in/out of the floating gate (FIG. 3). Such voltages are incompatible with the low 1-2 Volts commonly used in logic operation. To compensate for this disparity, large area charge pumps are often used to step up the voltage, consuming valuable on-chip real estate, and in some instances causing electromagnetic interference which can have a harmful effect on consumer devices with radio transceivers such as cellular phones.
Using a reversible change of phase (amorphous to/from crystalline) as a state variable circumvents the Flash scaling and radiation sensitivity problem. With phase change material (PCM) technology, the logic bit is stored as a large (100× or more) change in resistivity of certain materials that comes about with a structural change of phase. Such memory is currently operated at bit dimensions of approximately 90 nm, in the “lance” configuration shown in FIG. 3 [2]. This is based on a single via, typically made out of a TiN “heater” element with a GST (Ge2Sb2Te5) top.
“Lance”-PCM operation at low voltages compatible with logic is achievable, but the large current and energy needed to change the phase of the lance-PCM bit is still a significant drawback. This is due to the relatively large volume (10,000s of nm3) that must be Joule-heated. A recent improvement has been the development of individual phase-change material nanowires with diameters in the 30-100 nm range [3]. Unfortunately, little control can be maintained over the nanowire diameter, and hence on individual cells within an array, and even 30 nm diameter nanowires require (large) transition energies of the order 35 pJ (see Table I).
There are a few more memory (or circuit) switch alternatives. A good overview is provided by Ref. [9], including FeRAM (ferroelectric), MRAM (magnetic, spin-based), NEM (nano-electro-mechanical), and MIM (conductive filament bridging electrodes) devices. None appears to be a strong contender for a non-volatile switch with high on/off ratio and ultra-low energy requirement.
MRAM has high energy and area requirements, MIM and FeRAM have shown very challenging material issues, and none (except for NEMS) provide very good on/off behavior, i.e. the basic function of a true nanoscale switch with applicability beyond niche non-volatile memory. The NEMS switch is prototypically shown in FIG. 4, which in its current designs typically suffers from large voltage actuation requirements (5-25 V), and slow response times owed to the mechanical motion of the cantilever or nanobeam.
TABLE I depicts an illustrative embodiment of an order of magnitude comparison with modern state of the art (SOA) non-volatile memory (Flash, “lance” or PCM-nanowire), and a longer-term exotic alternative (NEMS) switch. The nanotube-PCM switch is expected to have the lowest transition energy & speed, and low voltage compatible with logic circuits. Simulations indicate a trade-off between the on/off ratio and the switching energy, which can be adjusted by engineering the phase-change material composition (depending on the application);
TABLE II depicts an illustrative embodiment of material parameters used in the simulations [7,13]; and
TABLE III depicts an illustrative embodiment of results of a computational study of the magnitude (E(a→c)) and variability (ΔE) in bit crystallization energy for a range of GST film thicknesses (d_GST) and nanotube radii (r_CNT). Thicker GST mid-layer increases the switching energy, but minimizes the impact of nanotube diameter variation over a relatively wide range.